The ADSP-21xx processors are all built upon a common core. Each processor combines the core DSP architecture-computation units, data address generators, and program sequencer-with differentiating features such as on-chip program and data memory RAM, a programmable timer, one or two serial ports.

• 25 MIPS, 40 ns Maximum Instruction Rate
• Separate On Chip busses for Program and data memory
• Dual Data Address Generator with Modulo and bit Reversing Addressing
• Efficient Program Sequencing with Zero-Overhead Looping: Single Cycle Loop Setup
• Automatic Booting of On Chip Program Memory from Byte -Wide External Memory (eg, EPROM)
• Double -Buffered Serial Ports with Companding hardware, Automatic Data , Buffering , and Multichannel Operation