The 40 GBit/s 4:1 multiplexer SHF 4005 A uses three 2:1 multiplexers to generate a 40 GBit/s data signal from four 10 GBit/s signals which are multiplexed to two 20 GBit/s signals. A 20 GHz clock input signal drives the output multiplexer while the two input multiplexers are driven by a 10 GHz clock signal generated by a 20 GHz divide by two circuit.

Two push-button / IEC - bus controlled delay lines allow to tune the phase shift of the input data signal for optimum performance of the output signal eye diagram. The actual delay is shown on a liquid crystal display having a resolution of 1 ps. The output signals are fed to two SHF 104 P line drivers which are tuned for optimum pulse performance at the end of the two 0.5 m low loss high precision cable assemblies which are supplied with the instrument.

The very low risetime of the multiplexer in connection with the pulse shaping 40 GHz amplifiers generates excellent 40 GBit/s eye pattern diagrams and allows an easy testing of ultra high speed components and their assembly into complex communication systems.

Complete specifications available upon request. "