The Logic Analyzer is designed to observe successive bytes (8-bit words) on any 8-bit bus. The Logic Analyzer operation is divided into two distinct parts: data acquisition and data display.

The data acquisition is controlled using a push button and can be triggered by an internal or external signal. During data acquisition incoming, 8-bit words are stored in the Logic Analyzer's memory until full. The memory  capacity is 2048 8-bit words. A clock signal is required to carry out the data acquisition. The data in memory is stored until a new data acquisition is carried out or until the power is turned off.

Once data acquisition is completed, the Logic Analyzer automatically proceeds with data display. The Logic Analyzer produces X-Y signals which allow observation on an oscilloscope screen of a group of 8-bit words stored in its memory. Each group or memory segment contains sixteen 8-bit words. The memory segment observed is selected through the use of push buttons. The number of the selected segment can be displayed on a 2-digit hexadecimal display. This display can also be used to obtain the hexadecimal representation of the 8-bit word present at the data input of the Logic Analyzer. The display on the oscilloscope screen (not included) consists of 8 horizontal traces. Each of these traces represent 1 bit of the 8-bit words. The lower trace represents the least significant bit (LSB) whereas the upper trace represents the most significant bit (MSB).

Specifications

Power Requirements: Connection to the Enclosure / Supply Regulator, Model 9420 (not included)

Clock Input
Frequency: 1 MHz maximum
Data Input: 8-bit parallel
Memory: 2K x 8-bit
X and Y Outputs: 8-level multiple signal to oscilloscope
Hexadecimal Display: 2-digit

Indicators
Indicators: Acquiring data
Trigger Ready: Trigger ready

Physical Characteristics
Dimensions (H x W x D) 83 x 142 x 212 mm (3.3 x 5.6 x 8.3 in)
Net Weight 0.9 kg (2 lb)